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NXP Semiconductors
PCA9530
2-bit I 2 C-bus LED dimmer
6.6 External RESET
A reset can be accomplished by holding the RESET pin LOW for a minimum of t w(rst) . The
PCA9530 registers and I 2 C-bus state machine will be held in their default states until the
RESET input is once again HIGH.
This input requires a pull-up resistor to V DD if no active connection is used.
7. Characteristics of the I 2 C-bus
The I 2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 6 ).
SDA
SCL
data line
stable;
change
of data
Fig 6.
Bit transfer
data valid
allowed
mba607
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is de?ned as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is de?ned as the STOP
condition (P) (see Figure 7 ).
SDA
SCL
S
START condition
P
STOP condition
mba608
PCA9530_3
Fig 7.
De?nition of START and STOP conditions
? NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 26 February 2009
7 of 24
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